An Overview On VLSI Design Flow & FPGAs

The IETE Student Branch and IEDC ASET in association with the department of Electronics and Communication Engineering organized a session on “An Overview on VLSI Design Flow and FPGAs” on 3rd February 2025 at Visvesvaraya Hall. Dr. Harish Ram, Associate Professor at Amrita Vishwa Vidyapeetham, Coimbatore, conducted the session attended by S4, S6, and S8 ECE students. The event was coordinated by Dr. Aneesh K (ECE), Lakshmy Suresh (EEE), and student coordinator Ashrin (S6 ECE).

The event was inaugurated by Dr. P.R. Suresh, with felicitations from Dr. Krishnakumar Kishore (Vice Principal) and Dr. V. Balamurugan (HOD/ECE). Dr. Harish Ram discussed VLSI fundamentals, design flow, and FPGA applications. A hands-on demonstration using Xilinx Vivado was provided, highlighting FPGA design flow.

The session covered:

• VLSI Design Flow: Overview of design steps, including specification, RTL design, synthesis, and verification

• FPGA Basics: Introduction to FPGA architecture and its advantages in modern applications.

• Hardware Description Languages (HDLs): Brief discussion on VHDL and Verilog for FPGA programming.

The session covered VLSI and FPGA design flow basics, emphasizing the importance of VLSI in today’s technological landscape. The need for VLSI in modern applications was highlighted, along with insights into career opportunities in the semiconductor industry. Students actively participated in discussions, making the event highly informative and engaging. A vote of thanks concluded the event.